1. Field of the Invention:
This invention relates generally to digital data processing systems, and in particular, to a read only memory (ROM) fabricated with insulated gate field effect transistors such as metal oxide semiconductor field effect transistors (MOSFET) in integrated circuit form.
2. Description of the Prior Art:
The logic of any data manipulating system may be partitioned into control logic and data path logic. In conventional arrangements the control logic is constructed in a matrix of Boolean logic gates. This matrix translates function codes, sequence counts, and other information about the state of a data path logic into control levels, or if gated with a timing pulse, into control signals. According to certain control logic arrangements, for example microprogramming, the control logic is implemented by a read only memory, the outputs of which become the control levels or, if gated with a timing pulse, the control signals for the system. Among the several advantages which microprogramming offers is the minimum geometry afforded by the control logic which is contained in a memory element which is relatively densely packed.
Of particular interest to the present invention is a read only memory in which the memory elements are comprised of MOSFET devices. The designation MOSFET refers to a class of semiconductor devices which includes, for example, a field effect transistor having a metal gate or other conductive material insulated from a silicon or other semiconductor substrate by an oxide or other insulating layer. Other known MOSFET devices utilize an insulating layer such as silicon nitride as opposed to an oxide layer. Thus the term MOSFET, or simply MOS as may be used herein, is used in the general or generic sense and indicates a general class of devices which may be otherwise referred to as field effect devices, insulated gate devices and/or surface effect devices. Such devices may be physically characterized as having first and second regions of a first conductivity type separated by an intermediate region of the opposite conductivity type, over which an insulated gate is disposed. By applying a voltage of the proper polarity to the gate, the surface of the intermediate region is effectively caused to change conductivity type between the first and second regions.
It is well known in the art that circuit logic functions may be implemented by MOS devices. In particular, complex MOS logical circuits may be constructed from basic logic blocks such as NAND and NOR gates. The parallel arrangement of MOS devices in a simple NOR circuit lends itself well to MOS integrated circuitry, as disclosed in U.S. Pat. No. 3,541,543. In such parallel integrated circuitry, it is apparent that available space may be utilized more efficiently through the use of shared diffused regions and the inherent self-isolation properties of MOS devices. However, in conventional silicon gate read only memory structures in which simple NOR logic is utilized, one metal-to-diffusion contact is required per ROM bit or per two ROM bits. Also, one interweaved power supply line is required for every two row lines. In conventional metal gate read only memory structures in which simple NOR logic is utilized, one power supply line is required for every two column lines.
There remains considerable interest in minimizing the geometry of ROM structures to provide improved performance and higher packing density. The following patents illustrate the state of the logic circuit art in which MOSFET devices are utilized to achieve these and other objects: Rizzi et al. U.S. Pat. No. 3,733,690 discloses a read only memory matrix having back-to-back PN junctions between each inner section of rows and columns. One junction of selected connections are electrically shorted to program the ROM by establishing single diode or junction connections at predetermined intersections. Heimbigner U.S. Pat. No. 3,746,882 teaches the use of field effect transistors with series connected gates in an input synchronizing circuit having NAND gates. Proebsting U.S. Pat. No. 3,775,963 teaches the use of enhancement and depletion field effect transistors with series connected gates in a logic inverter for integrated circuits. NAND gates are formed by providing additional enhancement mode devices between the output of an inverter stage and the source voltage. Mai et al U.S. Pat. No. 3,898,105 discloses method and structure related to MOS devices suitable for use as matrix elements in a ROM constructed according to the teachings of the present invention.